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MPC8240RZUPNS/D Rev. 0, 7/2002 MPC8240 Part Number Specification for the XPC8240RZUnnnx Series
Motorola Part Number Affected: XPC8240RZU250x
This document describes part-number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC8240 Integrated Processor Hardware Specifications (Order No. MPC8240EC/D). Specifications provided in this document supersede those in the MPC8240 Integrated Processor Hardware Specifications, Rev.1.0 or later, for the part numbers listed in Table A only. Specifications not addressed herein are unchanged. Because this document is frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola sales office for the latest version. Note that headings and table numbers in this document are not consecutively numbered. They are intended to correspond to the heading or table affected in the general hardware specification. The part number addressed in this document is listed in Table A. For more detailed ordering information see Section 1.8, "Ordering Information."
Table A. Part Number Addressed by This Data Sheet
Operating Conditions Motorola Part Number XPC8240RZU250x CPU Frequency 250 MHz VDD 2.625 125 mV TJ (C) Significant Differences from Hardware Specification
0 to 105 Modified voltage specifications to achieve 250 MHz
Note: The X prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
Features
1.2 Features
This section summarizes changes to the features of the MPC8240 described in the MPC8240 Integrated Processor Hardware Specifications. * Power management -- 2.625-V processor core
1.3 General Parameters
This section summarizes changes to the general parameters of the MPC8240 described in the MPC8240 Integrated Processor Hardware Specifications. * Core power supply 2.625 V 125 mV DC nominal
1.4.1. DC Electrical Characteristics
Table 2 provides the recommended operating conditions for the MPC8240 part number described herein.
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MPC8240 Part Number Specification for the XPC8240RZUnnnx Series
MOTOROLA
General Parameters Table 2. Recommended Operating Conditions
Characteristic Supply voltage Supply voltage for PCI and standard bus standards Supply voltages for memory bus drivers PLL supply voltage--CPU core logic PLL supply voltage--peripheral logic DLL supply voltage PCI reference Symbol VDD OVDD GVDD AVDD AVDD2 LAVDD LVDD Recommended Value 2.625 5% 3.3 0.3 3.3 5% 2.625 5% 2.6255 5% 2.625 5% 5.0 5% 3.3 0.3 Input voltage LVDD input tolerant signals All other inputs Die-junction temperature Tj Vin 0 to 3.6 or 5.75 0 to 3.6 0 to 105 Unit V V V V V V V V V V C Notes 4, 6 6 8 4, 6 4, 7 4, 7 9, 10 9, 10 2, 3 5
Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. These signals are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3- or 5.0-V DC power supply. 3. LVDD input tolerant signals: PCI interface, EPIC control, and OSC_IN signals. 4. See Section 1.8, "Ordering Information," for details on a modified voltage (VDD) version device. Cautions: 5. Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2/LAVDD) by more than 2.5 V at all times, including during power-on reset. 6. OVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 1.8 V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. VDD/AVDD/AVDD2/LAVDD must not exceed OVDD by more than 0.6 V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 8. GVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 1.8 V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 9. LVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 5.4 V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 10. LVDD must not exceed OVDD by more than 3.6 V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
1.4.1.5 Power Characteristics
Table 5 provides power consumption data for the MPC8240.
MOTOROLA
MPC8240 Part Number Specification for the XPC8240RZUnnnx Series
3
PLL Configuration Table 5. Preliminary Power Consumption
PCI Bus Clock/Memory Bus Clock CPU Clock Frequency (MHz) Mode 33/66/ 233 Typical Max--FP Max--INT Doze Nap Sleep 3.4 3.8 3.4 2.2 700 500 33/83/ 250 3.6 4.1 3.7 2.4 800 500 33/100/ 200 3.2 3.6 3.3 2.2 900 500 33/100/ 250 3.7 4.2 3.8 2.6 900 500 66/100/ 200 3.2 3.6 3.4 2.2 900 800 66/100/ 250 3.8 4.3 3.8 2.6 900 800 W W W W mW mW 1, 5 1, 2 1, 3 1, 4, 6 1, 4, 6 1, 4, 6 Unit Notes
I/O Power Supplies Mode Typ--OVDD Typ--GVDD Minimum 200 300 Maximum 600 900 Units mW mW Notes 7, 8 7, 9
Notes: 1. The values include VDD, AVDD, AVDD2, and LAVDD but do not include I/O supply power; see Section 1.7.2, "Power Supply Sizing," in the MPC8240 Integrated Processor Hardware Specifications, for information on OVDD and GVDD supply power. One DIMM used for memory loading. 2. Maximum--FP power is measured at VDD = 2.625 V with dynamic power management enabled while running an entirely cache-resident, looping, floating point multiplication instruction. 3. Maximum--INT power is measured at VDD = 2.625 V with dynamic power management enabled while running entirely cache-resident, looping, integer instructions. 4. Power saving mode maximums are measured at VDD = 2.625 V while the device is in doze, nap, or sleep mode. 5. Typical power is measured at VDD = AVDD = 2.625 V, OVDD = 3.3 V where a nominal FP value, a nominal INT value, and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory are averaged. 6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled. 7. The typical minimum I/O power values were results of the MPC8240 performing cache resident integer operations at the slowest frequency combination of 33:66:166 (PCI:Mem:CPU) MHz. 8. The typical maximum OVDD value resulted from the MPC8240 operating at the fastest frequency combination of 66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros to PCI memory. 9. The typical maximum GVDD value resulted from the MPC8240 operating at the fastest frequency combination of 66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries to local memory. 10. Power consumption on the PLL supply pins (AVDD and AVDD2) and the DLL supply pin (LAVDD) less than 15 mW. This parameter is guaranteed by design and is not tested.
1.5
PLL Configuration
The MPC8240 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO) frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the MPC8240 is shown in Table 18.
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MPC8240 Part Number Specification for the XPC8240RZUnnnx Series
MOTOROLA
PLL Configuration Table 18. MPC8240 Microprocessor PLL Configurations
250 MHz Part 8, 9 Ref. PLL_ CFG [0:4] 2 00000 00001 00010 00011 00100 00101 00111 01000 01010 01100 01110 10000 10010 10100 10110 11000 11010 11100 11101 11110 11111 CPU 1 PCI Clock Input Periph Logic/Mem HID1[0:4] (PCI_SYNC_IN) Bus Clock Range Range (MHz) (MHz) 00110 11000 00101 00101 00101 00110 11000 11000 00111 00110 11000 00100 00100 11110 11010 11000 11010 11000 00110 01111 Not Usable 1F 11111 Off Off Notes: 1. The processor HID1 values only represent the multiplier of the processor's PLL (memory-to-processor multiplier); thus, multiple MPC8240 PLL_CFG[0:4] values may have the same processor HID1 value. This implies that system software cannot read the HID1 register and associate it with a unique PLL_CFG[0:4] value. 2. PLL_CFG[0:4] settings not listed (00110, 01001, 01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and 11011) are reserved. 3. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode. 4. In clock off mode, no clocking occurs inside the MPC8240 regardless of the PCI_SYNC_IN input. 5. Limited due to maximum memory VCO = 225 MHz. 6. Limited due to minimum CPU VCO = 200 MHz. 7. Limited due to minimum memory VCO = 100 MHz. 8. For clarity, range values are shown rounded down to the nearest whole number (decimal place accuracy removed). 9. Note that the 250-MHz part is available only in the XPC8240RZUnnnx number series. 33
6-56 5
Ratios 3, 4 CPU Clock Range (MHz) 188-250 225-250 100-112 PCI to Mem (Mem VCO) Multiplier 3 (6) 3 (6) 1 (4) Bypass 100-113 2 (8) Bypass Bypass 100-168 225-250 125-250 150-250 150-200 100-200 175-250 200-250 186-250 200-250 150-250 125-250 1 (4) 2 (4) 2 (4) 2 (4) 3 (6) 1.5 (3) 2 (4) 2 (4) 2.5 (5) 1 (2) 1.5 (3) 1.5 (3) Off Mem to CPU (CPU VCO) Multiplier 2.5 (5) 3 (6) 2 (8) 2 (8) 2 (8) 2.5 (5) 3 (6) 3 (6) 4.5 (9) 2.5 (5) 3 (6) 2 (4) 2 (4) 3.5 (7) 4 (8) 3 (6) 4 (8) 3 (6) 2.5 (5) Off
0 1 2 3 4 5 7 8 A C E 10 12 14 16 18 1A 1C 1D 1E
25-33 25-27 50-56
5
75-100 75-83 50-56 Bypass
25-28 5
50-56 Bypass Bypass 33-56 50-55 50-100 50-83 75-100 50-100 50-71 50-62 62-83 50-62 50-83 50-100
25-27 25-50 25-41 25-33 33-66 25-35 25-31 25-33 50 7-62 33 33
7-55 7-66
MOTOROLA
MPC8240 Part Number Specification for the XPC8240RZUnnnx Series
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Ordering Information
1.8
Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 1.8.1, "Part Numbers Fully Addressed by This Document."
1.8.1
Part Numbers Fully Addressed by This Document
Table 19 provides the Motorola part numbering nomenclature for the MPC8240. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code that refers to the die mask revision number.
Table 19. Motorola Part Numbering Nomenclature
XPC
Product Code XPC
nnnn
Part Identifier 8240
L
Process Descriptor
xx
Package
nnn
Processor Frequency 250
x
Application Modifier 2.625 V 125 mV 0 to 105C
x
Revision Level Contact local Motorola sales office
R = Part Spec. ZU = TBGA
1.8.2 Part Marking
Parts are marked as the example shown in Figure 28.
XPC8240R ZU250E MMMMMM ATWLYYWWA
8240 TBGA Notes: MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 28. Motorola Part Marking for TBGA Device
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MPC8240 Part Number Specification for the XPC8240RZUnnnx Series
MOTOROLA
Document Revision History
Document Revision History
Table B provides a revision history for this part number specification.
Table B. Document Revision History
Rev. No. 0 Initial release. Substantive Change(s)
MOTOROLA
MPC8240 Part Number Specification for the XPC8240RZUnnnx Series
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